Supercomputing Software and Hardware

Article # 1_2020

27 с.

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Igor A. Adamovich, Yuri A. Klimov
The JaSpe specializer: an algorithm of intra-procedural binding time analysis for programs in Java language subset

A binding-time analysis in partial evaluation aimed at optimizing programs divides software constructs into static and dynamic. A specializer executes static constructs, and transfer dynamic ones into the resulting code. Currently, partial evaluation is mainly used for the non-trivial compilation of programs without a compiler, with only an interpreter and a specializer. As previous studies have shown, the effectiveness of such an application of the partial evaluation method significantly depends on the quality of the program annotation obtained by performing the binding-time analysis.
The paper is devoted to the features of the binding-time analysis algorithm. The features that arose during algorithm implementation for the widespread object-oriented Java language within the JaSpe specializer developed by the authors of this publication. The paper describes the basic concepts of the binding-time analysis implemented and the intra-procedural version of the algorithm. The article also discusses the algorithm details related to the program constructs that use reference data types.
Apart from previous counterparts for object-oriented languages, this algorithm non-trivially handles some language constructs: branches (if, switch), loops (for, while, do), and block instructions that contain a sequence of other instructions. Unlike the similar algorithms that work with imperative and functional languages, the considered algorithm uses the BT-objects, which allow specializer to obtain more accurate annotation (with a higher fraction of static constructs) when processing object-oriented programs. Another feature of this algorithm is the focus on interactivity and readability of results. (In Russian)

Key words: modern programming languages, static program analysis, program transformation, metaprogramming, mixed computation, interactive specialization.

article citation

 DOI

https://doi.org/10.25209/2079-3316-2020-11-1-3-29

Article # 3_2020

22 с.

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Igor A. Adamovich, Yuri A. Klimov
An FPGA packet communication protocol

When creating computer boards with FPGA or application-specific chips, it is often needed to connect several chips together. Existing available buses do not have all the properties required by the authors’ task at hand: packet transmission, using a small number of GPIO pins, sufficient bandwidth.
A packet communication protocol is presented that uses GPIO pins and has bandwidth up to 10 MB/s at frequency of 20 MHz.

Key words: half-duplex communication, credit-based flow control, data serialization/deserialization, finite state machine, shift register, hardware description language.

article citation

 DOI

DOI: https://doi.org/10.25209/2079-3316-2020-11-1-57-78