PROGRAM SYSTEMS: THEORY AND APPLICATIONS

12+

Online Scientific Journal published by the Ailamazyan Program Systems Institute of the Russian Academy of Sciences

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• Содержание выпуска •
• Software and Hardware for Distributed Systems and Supercomputers •
• Mathematical Foundations of Programming •
• Methods for Optimal Control and Control Theory •
• Artificial Intelligence, Intelligence Systems, Neural Networks •
• Supercomputing Software and Hardware •

Supercomputing Software and Hardware

Responsible for the Section: Sergei Abramov, Dr. Phys.-Math.Sci., corresponding member of RAS

On the left: assigned number of the paper, submission date, the number of A5 pages contained in the paper,
and the reference to the full-text PDF .

Article # 40_2015

15 с.

PDF

submitted on 16th Nov 2015 displayed on website on 07th Dec 2015

Nikolay Dikarev, Boris Shabanov, Aleksandr Shmelëv
Fused Multiply-Adders Using in Vector Dataflow Processor

Dataflow processor is able to issue up to 16 instructions per clock in contrary to 4–6 instructions per clock for best von-Neumann processor design. Simulation of our vector dataflow processor shows that matrix multiplication performance reaches 256 flops per clock on less then eight instructions per clock issue and can keep almost peak performance on much smaller matrix dimensions compared to traditional processor. Advantages and disadvantages of floating point fused multiply-add execution units are also analyzed when using in our vector dataflow processor design. (In Russian).

Key words: Supercomputer; vector processor; dataflow rchitecture; performance evaluation; fine grained parallelism; fused multiply-adders.

article citation

http://psta.psiras.ru/read/psta2015_4_227-241.pdf

DOI

https://doi.org/10.25209/2079-3316-2015-6-4-227-241

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