Hardware and software for distributed and supercomputer systems
Research Article
Cyclic pipeline systems
Igor Alekseevich Adamovich1
, Yuri Andreevich Klimov2
| 1 | Ailamazyan Program Systems Institute of RAS, Ves'kovo, Russia |
| 2 | Keldysh Institute of Applied Mathematics of RAS, Moscow, Russia |
| 1 |
i.a.adamovich@gmail.com |
Abstract. One of the most efficient ways to organize calculations on ASIC or FPGA is the creation of non-stallable pipelines. However, for some computing circuits, the resulting pipeline may be too large for available ASIC or FPGA resources. The authors propose a method for constructing cyclic pipelines, in which data flow control is based on counters and does not depend on the data being transmitting along the pipeline. We proposed the method makes it possible to build more compact non-stallable pipelines. One of the main details of method is to use cycle ratio equal to the number of times the data must go through the loop, after which the pipeline converts the data into the desired result. (In Russian).
Keywords: pipeline, ASIC, FPGA, integrated circuit, periodicity, queue, credit
MSC-2020
94-05; 94C30
For citation: Igor A. Adamovich, Yuri A. Klimov. Cyclic pipeline systems. Program Systems: Theory and Applications, 2023, 14:4, pp. 67–89. (In Russ.). https://psta.psiras.ru/2023/4_67-89.
Full text of article (PDF): https://psta.psiras.ru/read/psta2023_4_67-89.pdf.
The article was submitted 08.11.2023; approved after reviewing 29.11.2023; accepted for publication 29.11.2023; published online 13.12.2023.
